This paper presents a 2-stage pipelined-SAR ADC with artificial-neural-network (ANN) based digital calibration algorithm to calibrate the mismatch error in the

$1^{\mathrm {st}}$

-stage capacitive DAC (CDAC) and the inter-stage gain error (IGE) together. Previous ANN-based calibration schemes suffer from excessive power and hardware overhead due to the large number of network parameters. To facilitate hardware implementation, the proposed algorithm only requires

$N_{1}+1$

input parameters (

$N_{1}$

is the resolution of the

$1^{\mathrm {st}}$

-stage SAR ADC), in which the overall output of the

$2^{\mathrm {nd}}$

-stage SAR ADC is combined into a single parameter. In addition, the ANN utilizes a single-neuron hidden layer with linear activation function to calculate the actual bit weight of the ADC, remarkably reducing the hardware overhead and power consumption of the calibration circuit. The prototype 12-bit, 250 MS/s pipelined-SAR ADC with “loop-unrolled” architecture is implemented in 40-nm CMOS, in which a ring amplifier with improved bias circuit is used to realize a robust closed-loop gain for residue amplification. With the ANN-based calibration circuit implemented in an FPGA, the calibrated ADC achieves the SNDR of 65.0 dB and the SFDR of 84.0 dB at Nyquist input (124 MHz), with a Schreier figure of merit of 169.0 dB and a Walden figure of merit of 14.0 fJ/conv-step. The ADC core consumes 4.95 mW, with an active area of only 0.013 mm2.

Nannan Li

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