Athanasios T. Ramkaj

A 1.25-GS/s 7-b SAR ADC With 36.4-dB SNDR at 5 GHz Using Switch-Bootstrapping, USPC DAC and Triple-Tail Comparator in 28-nm CMOS

Athanasios T. Ramkaj, Maarten Strackx, Michiel Steyaert et al. · IEEE Journal of Solid-State Circuits · 2018 · 112 citations

Triple-tail Comparator, Sar Logic, Ghz Using Switch-bootstrapping +8

A 5-GS/s 158.6-mW 9.4-ENOB Passive-Sampling Time-Interleaved Three-Stage Pipelined-SAR ADC With Analog-Digital Corrections in 28-nm CMOS

Athanasios T. Ramkaj, Juan Carlos Pena Ramos, Marcel Pelgrom et al. · IEEE Journal of Solid-State Circuits · 2020 · 79 citations

Analog-digital Corrections, Engineering, Calibration +11

A 28 nm CMOS Triple-Latch Feed-Forward Dynamic Comparator With <27 ps / 1 V and <70 ps / 0.6 V Delay at 5 mV-Sensitivity

Athanasios T. Ramkaj, Marcel Pelgrom, Michiel Steyaert et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 2022 · 27 citations

Dynamic Latched Comparator, High-gain Three-stage Configuration, Triple-latch Arrangement +9

A 13.5-Gb/s 5-mV-Sensitivity 26.8-ps-CLK–OUT Delay Triple-Latch Feedforward Dynamic Comparator in 28-nm CMOS

Athanasios T. Ramkaj, Michiel Steyaert, Filip Tavernier · IEEE Solid-State Circuits Letters · 2019 · 26 citations

Engineering, Vlsi Design, 28-Nm Cmos +8

A 13.5-Gb/s 5-mV-Sensitivity 26.8-ps-CLK–OUT Delay Triple-Latch Feedforward Dynamic Comparator in 28-nm CMOS

Athanasios T. Ramkaj, Michiel Steyaert, Filip Tavernier · 2019 · 20 citations

Engineering, Vlsi Design, 28-Nm Cmos +7