Nils Wistoff

A “New Ara” for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design

Matteo Perotti, Matheus Cavalcante, Nils Wistoff et al. · 2022 · 62 citations

Landmark Chips, Array Computing, Engineering +15

Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-Based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET

Gianna Paulin, Paul Scheffler, Thomas Benz et al. · 2024 · 19 citations

Microarchitectural Timing Channels and their Prevention on an Open-Source 64-bit RISC-V Core

Nils Wistoff, Moritz Schneider, Frank K. Gürkaynak et al. · 2021 · 15 citations

Engineering, Information Security, Computer Architecture +18

Systematic Prevention of On-Core Timing Channels by Full Temporal Partitioning

Nils Wistoff, Moritz Schneider, Frank K. Gürkaynak et al. · IEEE Transactions on Computers · 2022 · 13 citations

On-Demand Redundancy Grouping: Selectable Soft-Error Tolerance for a Multicore Cluster

Michael Rogenmoser, Nils Wistoff, Pirmin Vogel et al. · 2022 · 12 citations · Full text