V. K. Tomar

Design of 10T SRAM cell with improved read performance and expanded write margin

Ashish Sachdeva, V. K. Tomar · IET Circuits Devices & Systems · 2020 · 48 citations · Full text

Engineering, Computer Engineering, Electrical Engineering +17

Design of a Stable Low Power 11-T Static Random Access Memory Cell

Ashish Sachdeva, V. K. Tomar · Journal of Circuits Systems and Computers · 2020 · 47 citations

Engineering, Computer Engineering, Electrical Engineering +17

Performance Evaluation of 6T, 7T, 8T, and 9T SRAM cell Topologies at 90 nm Technology Node

Deepak Mittal, V. K. Tomar · 2020 · 45 citations

Engineering, Computer Engineering, Electrical Engineering +14

Design of multi-cell upset immune single-end SRAM for low power applications

Ashish Sachdeva, V. K. Tomar · AEU - International Journal of Electronics and Communications · 2020 · 44 citations

Engineering, Computer Engineering, Electrical Engineering +13

A Schmitt-trigger based low read power 12T SRAM cell

Ashish Sachdeva, V. K. Tomar · Analog Integrated Circuits and Signal Processing · 2020 · 42 citations

Engineering, Computer Engineering, Electrical Engineering +14