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Publications
1
Citations
12
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Active since
2009
Vishwanath Patel is an author specializing in timing analysis, reconfigurable logic blocks, and configurable logic blocks.
Publications per year
2009–2009
FPGA IMPLEMENTATION OF DES USING PIPELINING CONCEPT WITH SKEW CORE KEY-SCHEDULING
Vishwanath Patel, R. C. Joshi, A.K Saxena et al. · 2009 · 12 citations
Engineering, Computer Engineering, Computer Science +17
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