J. P. Anita

Efficient don't-care filling method to achieve reduction in test power

V. Sinduja, Siddharth Raghav, J. P. Anita · 2015 · 17 citations

Engineering, Computer Engineering, Electrical Engineering +17

Design of a low power, high speed double tail comparator

S Aakash, A. Anisha, Geeta Das et al. · 2017 · 17 citations

Engineering, Computer Engineering, Electrical Engineering +17

Genetic algorithm based test pattern generation for multiple stuck-at faults and test power reduction in VLSI circuits

J. P. Anita, P. T. Vanathi · 2014 · 13 citations

Architecture, Computer Engineering, Evolutionary Design +16

A zero suppressed binary decision diagram-based test set relaxation for single and multiple stuck-at faults

Navya Mohan, J. P. Anita · International Journal of Mathematical Modelling and Numerical Optimisation · 2016 · 12 citations

Engineering, Computer Engineering, Computer Science +12

Modified carry select adder for power and area reduction

T. Abhiram, T. Ashwin, Batta Sivaprasad et al. · 2017 · 11 citations

Engineering, Computer Engineering, Computer Science +16