H. Miyatake

A design for high-speed low-power CMOS fully parallel content-addressable memory macros

H. Miyatake, Masanori Tanaka, Yumi Mori · IEEE Journal of Solid-State Circuits · 2001 · 124 citations

Hardware Security, Electrical Engineering, Engineering +14

A parallel processing chip with embedded DRAM macros

T. Sunaga, H. Miyatake, Koji Kitamura et al. · IEEE Journal of Solid-State Circuits · 1996 · 25 citations

Manycore Processor, Engineering, Dram Design +14

Optimizing Write Current and Write Power Consumption in Magnetoresistive Random Access Memories by Using Generalized Asteroid Curves

H. Miyatake · Japanese Journal of Applied Physics · 2007 · 20 citations

Non-volatile Memory, Engineering, Computer Architecture +19

DRAM macros for ASIC chips

T. Sunaga, H. Miyatake, Koji Kitamura et al. · IEEE Journal of Solid-State Circuits · 1995 · 19 citations

Hardware Security, Electrical Engineering, Engineering +13