Walker J. Turner

ParaGraph: Layout Parasitics and Device Parameter Prediction using Graph Neural Networks

Haoxing Ren, George F. Kokai, Walker J. Turner et al. · 2020 · 98 citations

Engineering, Machine Learning, Neural Networks (Machine Learning) +23

A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator

John W. Poulton, John Wilson, Walker J. Turner et al. · IEEE Journal of Solid-State Circuits · 2018 · 61 citations

Low-power Electronics, On-package Communication, Engineering +9

A 0.297-pJ/Bit 50.4-Gb/s/Wire Inverter-Based Short-Reach Simultaneous Bi-Directional Transceiver for Die-to-Die Interface in 5-nm CMOS

Yoshinori Nishi, John W. Poulton, Walker J. Turner et al. · IEEE Journal of Solid-State Circuits · 2023 · 45 citations

Engineering, Device Integration, 5-Nm Cmos +16

A 1.17pJ/b 25Gb/s/pin ground-referenced single-ended serial link for off- and on-package communication in 16nm CMOS using a process- and temperature-adaptive voltage regulator

John Wilson, Walker J. Turner, John W. Poulton et al. · 2018 · 42 citations

Hardware Security, Electrical Engineering, On-package Communication +14

Parasitic-Aware Analog Circuit Sizing with Graph Neural Networks and Bayesian Optimization

Mingjie Liu, Walker J. Turner, George F. Kokai et al. · 2021 · 38 citations

Engineering, Machine Learning, Analog Design +16