Carlos Briseno-Vidrios

A 43-mW MASH 2-2 CT $\Sigma \Delta$ Modulator Attaining 74.4/75.8/76.8 dB of SNDR/SNR/DR and 50 MHz of BW in 40-nm CMOS

Alexander Edward, Qiyuan Liu, Carlos Briseno-Vidrios et al. · IEEE Journal of Solid-State Circuits · 2016 · 41 citations

Engineering, Electrical Engineering, Analog Electronics +16

Low-Power ${G}_{{m}}{-}C$ Filter Employing Current-Reuse Differential Difference Amplifiers

John Mincey, Carlos Briseno-Vidrios, José Silva-Martínez et al. · IEEE Transactions on Circuits & Systems II Express Briefs · 2016 · 37 citations · Full text

Engineering, Electrical Engineering, Analog Electronics +16

A 75-MHz Continuous-Time Sigma–Delta Modulator Employing a Broadband Low-Power Highly Efficient Common-Gate Summing Stage

Carlos Briseno-Vidrios, Alexander Edward, Ayman Shafik et al. · IEEE Journal of Solid-State Circuits · 2016 · 27 citations

Engineering, Electrical Engineering, Analog Electronics +16

A 13-Bit 260MS/s Power-Efficient Pipeline ADC Using a Current-Reuse Technique and Interstage Gain and Nonlinearity Errors Calibration

Dadian Zhou, Carlos Briseno-Vidrios, Junning Jiang et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 2019 · 24 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 44-fJ/Conversion Step 200-MS/s Pipeline ADC Employing Current-Mode MDACs

Carlos Briseno-Vidrios, Dadian Zhou, Suraj Prakash et al. · IEEE Journal of Solid-State Circuits · 2018 · 18 citations

Engineering, Computer Engineering, Electrical Engineering +17