Jean Durupt - Concepedia

Author

Jean Durupt

Commissariat à l'Énergie Atomique et aux Énergies Alternatives

Also Known As

Durupt, Jean, J. Durupt, Jean Durupt

Publications

399

Citations

H-Index

Concepts

All Affiliations

Commissariat à l'Énergie Atomique et aux Énergies Alternatives CEA Grenoble Laboratoire d'Électronique des Technologies de l'Information Université Grenoble Alpes Institut polytechnique de Grenoble

About

Jean Durupt is an author at Commissariat à l'Énergie Atomique et aux Énergies Alternatives specializing in computer engineering, engineering, and computer architecture.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Computer Engineering	9	9	350
2	Engineering	8	8	335
3	Computer Science	4	4	177
4	Electrical Engineering	4	4	215
5	Education	1	1	15

Jean Durupt

Publications

362

Citations

H-Index

Page 1

	Year	Citations
IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management Pascal Vivet, Èric Guthmuller, Yvain Thonnart, IEEE Journal of Solid-State Circuits Artificial IntelligenceEngineeringVlsi DesignComputer ArchitectureComputing Capabilities	2020	118
A Telecom Baseband Circuit based on an Asynchronous Network-on-Chip Didier Lattard, Édith Beigné, Christian Bernard, Wireless CommunicationsSystem On ChipBaseband Processing ArchitectureEngineeringMixed-signal Integrated Circuit	2007	61
2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm<sup>2</sup> Inter-Chiplet Interconnects and 156mW/mm<sup>2</sup>@ 82%-Peak-Efficiency DC-DC Converters Pascal Vivet, Èric Guthmuller, Yvain Thonnart, EngineeringVlsi DesignEnergy EfficiencyComputer ArchitectureIntegrated Circuits	2020	60
An asynchronous power aware and adaptive NoC based circuit Édith Beigné, F. Clermidy, Jean Durupt, Power-aware ComputingElectrical EngineeringEngineeringEdge ComputingComputer Engineering	2008	24
Design-for-test approach of an asynchronous network-on-chip architecture and its associated test pattern generation and application Xuan‐Tu Tran, Yvain Thonnart, Jean Durupt, IET Computers & Digital Techniques EngineeringComputer ArchitectureAsynchronous Noc ArchitectureDesign-for-test ApproachHardware Security	2009	23
A DFT Architecture for Asynchronous Networks-on-Chip Xuan‐Tu Tran, Jean Durupt, F. Bertrand, Hardware SecuritySystem On ChipTest ArchitecturesDft TechniquesEngineering	2006	21
A 0.8ma 50Hz 15b SNDR ΔΣ closed-loop 10g accelerometer using an 8/sup th/-order digital compensator Cyril Condemine, Nicolas Delorme, Jonathan Soen, Th/-order Digital CompensatorElectrostatic ActuationMeasurementData ConverterMixed-signal Integrated Circuit	2005	15
A Design-for-Test Implementation of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application Xuan‐Tu Tran, Yvain Thonnart, Jean Durupt, EngineeringComputer ArchitectureSystem-level DesignHardware SystemsHardware Security	2008	15
An ultra low power 130nm CMOS direct conversion transceiver for IEEE802.15.4 Carolynn Bernier, Frédéric Hameau, G. Billiot, Low-power ElectronicsIeee802.15.4 SpecificationElectrical EngineeringEngineeringAnalog-to-digital Converter	2008	13
IJTAG supported 3D DFT using chiplet-footprints for testing multi-chips active interposer system Jean Durupt, Pascal Vivet, Juergen Schloeffel	2016	12

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