Y.S. Dhillon

Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits

Y.S. Dhillon, A.U. Diril, Arghya Chatterjee · Design, Automation, and Test in Europe · 2005 · 120 citations · Full text

Hardware Security, Electrical Engineering, Physical Design (Electronics) +13

Analysis and optimization of nanometer CMOS circuits for soft-error tolerance

Y.S. Dhillon, A.U. Diril, Abhijit Chatterjee et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2006 · 85 citations

Low-power Electronics, Electrical Engineering, Engineering +13

Algorithm for Achieving Minimum Energy Consumption in CMOS Circuits Using Multiple Supply and Threshold Voltages at the Module Level

Y.S. Dhillon, A.U. Diril, Abhijit Chatterjee et al. · International Conference on Computer Aided Design · 2003 · 37 citations

Engineering, Vlsi Design, Power Optimization (Eda) +16

Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages

A.U. Diril, Y.S. Dhillon, Abhijit Chatterjee et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2005 · 33 citations

Engineering, Vlsi Design, Computer Architecture +16

Design of Adaptive Nanometer Digital Systems for Effective Control of Soft Error Tolerance

A.U. Diril, Y.S. Dhillon, Abhijit Chatterjee et al. · 2005 · 23 citations

Engineering, Vlsi Design, Concurrent Error Detection +23