Taeho Seong

16.2 A 76fs<inf>rms</inf> Jitter and –40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization

Juyeop Kim, Heein Yoon, Younghyun Lim et al. · 2019 · 59 citations

Engineering, Background Loop-gain Optimization, Radio Frequency +17

A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop Filter PLL Using a Fast Phase-Error Correction Technique

Yongsun Lee, Taeho Seong, Seyeon Yoo et al. · IEEE Journal of Solid-State Circuits · 2017 · 49 citations

Engineering, Vlsi Design, Clock Recovery +8

A 320-fs RMS Jitter and – 75-dBc Reference-Spur Ring-DCO-Based Digital PLL Using an Optimal-Threshold TDC

Taeho Seong, Yongsun Lee, Seyeon Yoo et al. · IEEE Journal of Solid-State Circuits · 2019 · 46 citations

Optimal-threshold Tdc, Low Jitter, Clock Recovery +9

An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally Spaced Voltage Comparators

Juyeop Kim, Younghyun Lim, Heein Yoon et al. · IEEE Journal of Solid-State Circuits · 2019 · 46 citations

Frequency Band, Engineering, Oscillators +10

A Low-Jitter and Low-Fractional-Spur Ring-DCO-Based Fractional-<i>N</i> Digital PLL Using a DTC’s Second-/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping ΔΣM

Chanwoong Hwang, Hangi Park, Yongsun Lee et al. · IEEE Journal of Solid-State Circuits · 2022 · 46 citations