Pavel V. Stepanov

Basic memory elements using DICE cells for fault-tolerant 28 nm CMOS RAM

V. Ya. Stenin, Pavel V. Stepanov · Russian Microelectronics · 2015 · 21 citations

Engineering, Computer Engineering, Electrical Engineering +17

Upset-resilient RAM on STG DICE memory elements with the spaced transistors into two groups

V. Ya. Stenin, Yu. V. Katunin, Pavel V. Stepanov · Russian Microelectronics · 2016 · 21 citations

Engineering, Computer Engineering, Electrical Engineering +11

Modeling the characteristics of trigger elements of two-phase CMOS logic, taking into account the charge sharing effect under exposure to single nuclear particles

Yu. V. Katunin, V. Ya. Stenin, Pavel V. Stepanov · Russian Microelectronics · 2014 · 20 citations

Engineering, Computer Engineering, Electrical Engineering +14

Design of logical elements for the 65-nm CMOS translation lookaside buffer with compensation of single events effects

V. Ya. Stenin, Artem V. Antonyuk, Pavel V. Stepanov et al. · 2017 · 15 citations

Engineering, Computer Engineering, Electrical Engineering +17

Mathematical Models and Applicable Technologies to Forecast, Analyze, and Optimize Quality and Risks for Complex Systems

Andrey Kostogryzov, V. S. Krylov, Andrey Nistratov et al. · 2011 · 14 citations

Business, Risk Management, Systems Engineering +17