K. Nadehara - Concepedia

Author

K. Nadehara

Also Known As

K. Nadehara, Kouhei Nadehara

Publications

215

Citations

H-Index

Concepts

All Affiliations

K. Nadehara is an author at NEC (Japan) specializing in computer architecture, computer engineering, and engineering.

#	Concept	H-Index	Publications	Citations
1	Engineering	7	7	143
2	Computer Engineering	7	7	143
3	Computer Architecture	7	7	143
4	Computer Science	5	5	94
5	Systems Engineering	1	1	14

K. Nadehara

Publications

143

Citations

H-Index

Page 1

	Year	Citations
A 100 MHz, 0.4 W RISC processor with 200 MHz multiply adder, using pulse-register technique S. Kozu, M. Daito, Yousuke Sugiyama, EngineeringVlsi DesignComputer ArchitectureSignal Processing ApplicationsProcessor Architecture	2002	30
Low-power multimedia RISC K. Nadehara, I. Kuroda, M. Daito, IEEE Micro EngineeringVlsi DesignV830 ChipMultimedia ProcessorBattery-powered Multimedia Systems	1995	29
Extended instructions for the aes cryptography and their efficient implementation K. Nadehara, M. Ikekawa, I. Kuroda Cryptographic PrimitiveEngineeringInformation SecurityCryptographic TechnologyComputer Architecture	2004	28
Radix-4 FFT implementation using SIMD multimedia instructions K. Nadehara, Takashi Miyazaki, I. Kuroda Consecutive 4EngineeringSimd Multimedia InstructionsHardware AccelerationMultimedia Signal Processing	1999	19
A 2000-MOPS embedded RISC processor with a Rambus DRAM controller Kazumasa Suzuki, M. Daito, Toshiaki Inoue, IEEE Journal of Solid-State Circuits Leaf CellsVlsi DesignEngineeringComputer ArchitectureEmbedded Systems	1999	14
A low-power, 32-bit RISC processor with signal processing capability and its multiply-adder K. Nadehara, M. Hayashida, I. Kuroda EngineeringVlsi DesignComputer ArchitectureSignal Processing CapabilityProcessor Architecture	2002	13
A 16-bit parallel MAC architecture for a multimedia RISC processor I. Kuroda, E. Murata, K. Nadehara, EngineeringMultimedia ProcessorHardware AlgorithmComputer ArchitectureProcessor Architecture	2002	10

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