John Vivalda

20 ${\hbox{kA/cm}}^{2}$ Process Development for Superconducting Integrated Circuits With 80 GHz Clock Frequency

Sergey K. Tolpygo, Daniel Yohannes, Richard T. Hunt et al. · IEEE Transactions on Applied Superconductivity · 2007 · 68 citations

Superconducting Material, Engineering, Process Development +18

ERSFQ 8-Bit Parallel Adders as a Process Benchmark

Alex F. Kirichenko, I. V. Vernik, John Vivalda et al. · IEEE Transactions on Applied Superconductivity · 2014 · 36 citations

Process Benchmark, Electrical Engineering, Mit Lincoln Lab +15

Planarized, Extendible, Multilayer Fabrication Process for Superconducting Electronics

Daniel Yohannes, Rick T. Hunt, John Vivalda et al. · IEEE Transactions on Applied Superconductivity · 2014 · 28 citations

Superconducting Material, Engineering, Multilayer Fabrication Process +18

Retargeting RSFQ cells to a submicron fabrication process

D.K. Brock, Alan M. Kadin, A.F. Kirichenko et al. · IEEE Transactions on Applied Superconductivity · 2001 · 25 citations

Miniaturization, Engineering, Vlsi Design +17

Diffusion Stop-Layers for Superconducting Integrated Circuits and Qubits With Nb-Based Josephson Junctions

Sergey K. Tolpygo, Denis Amparo, Richard T. Hunt et al. · IEEE Transactions on Applied Superconductivity · 2010 · 16 citations · Full text