Thomas Haine

SleepRunner: A 28-nm FDSOI ULP Cortex-M0 MCU With ULL SRAM and UFBR PVT Compensation for 2.6–3.6-<i>μ</i>W/DMIPS 40–80-MHz Active Mode and 131-nW/kB Fully Retentive Deep-Sleep Mode

David Bol, Maxime Schramme, Ludovic Moreau et al. · IEEE Journal of Solid-State Circuits · 2021 · 31 citations · Full text

Engineering, Computer Engineering, Electrical Engineering +17

Gradient importance sampling: An efficient statistical extraction methodology of high-sigma SRAM dynamic characteristics

Thomas Haine, Johan Segers, Denis Flandre et al. · 2018 · 21 citations · Full text

Engineering, Computer Engineering, Electrical Engineering +17

19.6 A 40-to-80MHz Sub-4μW/MHz ULV Cortex-M0 MCU SoC in 28nm FDSOI With Dual-Loop Adaptive Back-Bias Generator for 20μs Wake-Up From Deep Fully Retentive Sleep Mode

David Bol, Maxime Schramme, Ludovic Moreau et al. · 2019 · 18 citations

Engineering, Computer Engineering, Electrical Engineering +17

An 80-MHz 0.4V ULV SRAM macro in 28nm FDSOI achieving 28-fJ/bit access energy with a ULP bitcell and on-chip adaptive back bias generation

Thomas Haine, Quoc-Khoi Nguyen, François Stas et al. · 2017 · 13 citations

Engineering, Computer Engineering, Electrical Engineering +17