Kazushige Ayukawa

A dynamic-SDRAM-mode-control scheme for low-power systems with a 32-bit RISC CPU

Seiji Miura, Kazushige Ayukawa, Takao Watanabe · 2001 · 17 citations

Engineering, Computer Engineering, Computer Science +10

An access-sequence control scheme to enhance random-access performance of embedded DRAM's

Kazushige Ayukawa, Takao Watanabe, S. Narita · IEEE Journal of Solid-State Circuits · 1998 · 13 citations

Engineering, Computer Engineering, Computer Science +15

A modular architecture for a 6.4-Gbyte/s, 8-Mbit media chip

Takao Watanabe, R. Fujita, Kazumasa Yanagisawa et al. · 2002 · 11 citations

Engineering, Computer Engineering, Computer Science +13

A modular architecture for a 6.4-Gbyte/s, 8-Mb DRAM-integrated media chip

Takao Watanabe, R. Fujita, Kazumasa Yanagisawa et al. · IEEE Journal of Solid-State Circuits · 1997 · 11 citations

Engineering, Computer Engineering, Computer Science +16

Access optimizer to overcome the "future walls of embedded DRAMs" in the era of systems on silicon

Takao Watanabe, Kazushige Ayukawa, Seiji Miura et al. · 2003 · 10 citations

Engineering, Computer Engineering, Computer Science +15