Concepedia

Reiley Jeyapaul

RJ

Statistics

Publications

13

Citations

239

H-Index

11

Active since

2008

Affiliations

Arizona State University(Current)

Yonsei University

ARM (United Kingdom)

Reiley Jeyapaul is an author at Arizona State University specializing in computer architecture, engineering, and computer engineering.

Top concepts

EngineeringComputer ScienceComputer EngineeringComputer ArchitectureHardware SecurityProgram AnalysisParallel ComputingSoftware AnalysisEmbedded SystemsSystems Engineering

Publications per year

2008–2019

13

Publications

13

Quantitative Analysis of Control Flow Checking Mechanisms for Soft Errors

Aviral Shrivastava, Abhishek Rhisheekesan, Reiley Jeyapaul et al. · 2014 · 34 citations

Program Checking, Engineering, Error Control Technique +24

SPKM : A novel graph drawing based algorithm for application mapping onto coarse-grained reconfigurable architectures

Jonghee Yoon, Aviral Shrivastava, Sang‐Hyun Park et al. · 2008 · 32 citations

Engineering, Electronic Design Automation, Coarse-grained Reconfigurable Architectures +25

Cache vulnerability equations for protecting data in embedded processor caches from soft errors

Aviral Shrivastava, Jongeun Lee, Reiley Jeyapaul · 2010 · 22 citations

Engineering, Information Security, Continuous Technology Scaling +26

gemV: A validated toolset for the early exploration of system reliability

Karthik Tanikella, Yohan Koy, Reiley Jeyapaul et al. · 2016 · 22 citations

Software Maintenance, Software Reliability Testing, Engineering +27

Control Flow Checking or Not? (for Soft Errors)

Abhishek Rhisheekesan, Reiley Jeyapaul, Aviral Shrivastava · ACM Transactions on Embedded Computing Systems · 2019 · 22 citations · Full text

Program Checking, Engineering, Hardware Verification Language +23

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