Caaliph Andriamisaina

A 5500-frames/s 85-GOPS/W 3-D Stacked BSI Vision Chip Based on Parallel In-Focal-Plane Acquisition and Processing

Laurent Millet, Stéphane Chevobbe, Caaliph Andriamisaina et al. · IEEE Journal of Solid-State Circuits · 2019 · 28 citations

Engineering, Computer Architecture, Parallel In-focal-plane Acquisition +21

Bit-Width Aware High-Level Synthesis for Digital Signal Processing Systems

Bertrand Le Gal, Caaliph Andriamisaina, Emmanuel Casseau · 2006 · 16 citations

Hardware Security, Logic Synthesis, Engineering +15

High-Level Synthesis for Designing Multimode Architectures

Caaliph Andriamisaina, Philippe Coussy, Emmanuel Casseau et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2010 · 12 citations

Engineering, Computer Architecture, Dedicated Design Flow +19

An Efficient and Flexible Hardware Support for Accelerating Synchronization Operations on the STHORM Many-Core Architecture

Farhat Thabet, Yves Lhuillier, Caaliph Andriamisaina et al. · Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013 · 2013 · 11 citations

Cluster Computing, Engineering, Computer Architecture +20

HARS

Yves Lhuillier, Maroun Ojail, Alexandre Guerre et al. · ACM Transactions on Embedded Computing Systems · 2014 · 10 citations

Cluster Computing, Heterogeneous Computing, Engineering +15