D. Weiss

The on-chip 3-MB subarray-based third-level cache on an Itanium microprocessor

D. Weiss, John Wuu, V. Chin · IEEE Journal of Solid-State Circuits · 2002 · 68 citations

Engineering, Vlsi Design, Computer Architecture +16

The asynchronous 24MB on-chip level-3 cache for a dual-core Itanium-family processor

John Wuu, D. Weiss, Charles Morganti et al. · 2005 · 46 citations

Engineering, Vlsi Design, On-chip Level-3 Cache +19

32nm high-density high-speed T-RAM embedded memory technology

Rajesh Gupta, F. Nemati, Scott Robins et al. · 2010 · 20 citations

Non-volatile Memory, Engineering, Memory Design +17

A 2ns-read-latency 4Mb embedded floating-body memory macro in 45nm SOI technology

A.P. Singh, Michael Ciraula, D. Weiss et al. · 2009 · 15 citations

Non-volatile Memory, Engineering, Memory Design +20