Biswajit Baral

Study of effect of gate-length downscaling on the analog/RF performance and linearity investigation of InAs-based nanowire Tunnel FET

Sudhansu Mohan Biswal, Biswajit Baral, Debashis De et al. · Superlattices and Microstructures · 2016 · 56 citations

Engineering, Electrical Engineering, Materials Science +17

Simulation and comparative study on analog/RF and linearity performance of III–V semiconductor-based staggered heterojunction and InAs nanowire(nw) Tunnel FET

Sudhansu Mohan Biswal, Biswajit Baral, Debashis De et al. · Microsystem Technologies · 2017 · 36 citations

Engineering, Electrical Engineering, Materials Science +17

Analytical subthreshold modeling of dual material gate engineered nano-scale junctionless surrounding gate MOSFET considering ECPE

Sudhansu Mohan Biswal, Biswajit Baral, Debashis De et al. · Superlattices and Microstructures · 2015 · 34 citations

Engineering, Electrical Engineering, Materials Science +16

Radio frequency/analog and linearity performance of a junctionless double gate metal–oxide–semiconductor field-effect transistor

Biswajit Baral, Sudhansu Mohan Biswal, Debashis De et al. · SIMULATION · 2017 · 26 citations

Engineering, Electrical Engineering, Analog Electronics +16

Effect of gate‐length downscaling on the analog/RF and linearity performance of InAs‐based nanowire tunnel FET

Biswajit Baral, Sudhansu Mohan Biswal, Debashis De et al. · International Journal of Numerical Modelling Electronic Networks Devices and Fields · 2016 · 15 citations

Engineering, Electrical Engineering, Materials Science +17