Hoosung Cho

Vertical cell array using TCAT(Terabit Cell Array Transistor) technology for ultra high density NAND flash memory

Jae Hoon Jang, Han‐Soo Kim, Wonseok Cho et al. · Symposium on VLSI Technology · 2006 · 377 citations

Engineering, Computer Engineering, Electrical Engineering +17

Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30nm Node

Soon‐Moon Jung, Jaehoon Jang, Wonseok Cho et al. · 2006 · 113 citations

Engineering, Computer Engineering, Electrical Engineering +15

Highly reliable vertical NAND technology with biconcave shaped storage layer and leakage controllable offset structure

Won-seok Cho, Sun Il Shim, Jae Hoon Jang et al. · 2010 · 38 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 45nm 4Gb 3-Dimensional Double-Stacked Multi-Level NAND Flash Memory with Shared Bitline Structure

Ki‐Tae Park, Doogon Kim, Soonwook Hwang et al. · 2008 · 33 citations

Engineering, Computer Engineering, Electrical Engineering +14

A Fully Performance Compatible 45 nm 4-Gigabit Three Dimensional Double-Stacked Multi-Level NAND Flash Memory With Shared Bit-Line Structure

Kitae Park, Myounggon Kang, Soonwook Hwang et al. · IEEE Journal of Solid-State Circuits · 2009 · 21 citations

Engineering, Computer Engineering, Electrical Engineering +14