Görschwin Fey

On Acceleration of SAT-Based ATPG for Industrial Designs

Rolf Drechsler, Görschwin Fey, Andreas Glowatz et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2008 · 92 citations

Engineering, Electronic Design Automation, Conjunctive Normal Forms +16

Automatic Fault Localization for Property Checking

Görschwin Fey, Stefan Staber, Roderick Bloem et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2008 · 91 citations

Software Maintenance, Engineering, Verification +20

Synthesis of Fully Testable Circuits From BDDs

Rolf Drechsler, Junhao Shi, Görschwin Fey · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2004 · 64 citations

Hardware Security, Logic Synthesis, Reliability Engineering +15

Using unsatisfiable cores to debug multiple design errors

Andre Suelflow, Görschwin Fey, Roderick Bloem et al. · 2008 · 59 citations

Engineering, Hardware Verification Language, Verification +19

SWORD: A SAT like prover using word level information

Robert Wille, Görschwin Fey, Daniel Große et al. · 2007 · 47 citations

Engineering, Verification, Computer-aided Verification +22