B.S. Cherkauer

A unified design methodology for CMOS tapered buffers

B.S. Cherkauer, Eby G. Friedman · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 1995 · 111 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 65 nm 2-Billion Transistor Quad-Core Itanium Processor

Blaine Stackhouse, Sal Bhimji, Chris Bostak et al. · IEEE Journal of Solid-State Circuits · 2009 · 105 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache

Stefan Rusu, Simon Tam, H. Muljono et al. · IEEE Journal of Solid-State Circuits · 2007 · 98 citations

Engineering, Computer Engineering, Computer Science +17

A 65nm 2-Billion-Transistor Quad-Core Itanium® Processor

Blaine Stackhouse, B.S. Cherkauer, Mike Gowan et al. · 2008 · 62 citations

Engineering, Computer Engineering, Electrical Engineering +16

A hybrid radix-4/madix-8 low power signed multiplier architecture

B.S. Cherkauer, Eby G. Friedman · IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing · 1997 · 43 citations

Engineering, Computer Engineering, Computer Science +15