P.V. Anandmohan

High Throughput, low cost, Fully Pipelined Architecture for AES Crypto Chip

Nalini C. Iyer, P.V. Anandmohan, D.V. Poornaiah et al. · 2006 · 26 citations

Engineering, Aes Crypto Chip, High Throughput +17

An FPGA Based Performance Analysis of Pipelining and Unrolling of AES Algorithm

C. Nalini, Nagaraj, P.V. Anandmohan et al. · 2006 · 20 citations

Hardware Security, Data Encryption Standard, Engineering +15

Compact Designs of SubBytes and MixColumn for AES

C. Nalini, P.V. Anandmohan, D. V Poomaiah et al. · 2009 · 15 citations

Engineering, Composite Field, Hardware Algorithm +20

Mix/InvMixColumn decomposition and resource sharing in AES

Nalini C. Iyer, Deepa, P.V. Anandmohan et al. · 2010 · 11 citations

Engineering, Advanced Computing, Hardware Algorithm +16