J. Benkoski

Timing verification using statically sensitizable paths

J. Benkoski, E. Vanden Meersch, Luc Claesen et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1990 · 86 citations

Circuit Complexity, Engineering, Reachability Problem +20

A New Approach to Hierarchical and Statistical Timing Simulations

J. Benkoski, Andrzej J. Strojwas · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1987 · 40 citations

Hardware Modeling, Engineering, Computer Architecture +18

Yield optimization of analog ICs using two-step analytic modeling methods

Carlo Guardiani, P. Scandolara, J. Benkoski et al. · IEEE Journal of Solid-State Circuits · 1993 · 20 citations

Numerical Analysis, Engineering, Electronic Design Automation +20

Applying a submicron mismatch model to practical IC design

Carlo Guardiani, A. Tomasini, J. Benkoski et al. · 2002 · 15 citations

3D Ic Architecture, Electrical Engineering, Physical Design (Electronics) +14

Timing verification by formal signal interaction modeling in a multi-level timing simulator

J. Benkoski, Andrzej J. Strojwas · 1989 · 12 citations · Full text

Hardware Modeling, Engineering, High Level Models +22