Ajay N. Bhoj

Design of Logic Gates and Flip-Flops in High-Performance FinFET Technology

Ajay N. Bhoj, Niraj K. Jha · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2013 · 74 citations

Device Modeling, Electrical Engineering, Nonplanar Cmos Devices +14

3-D-TCAD-Based Parasitic Capacitance Extraction for Emerging Multigate Devices and Circuits

Ajay N. Bhoj, Rajiv Joshi, Niraj K. Jha · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2013 · 55 citations

Device Modeling, 3D Ic Architecture, Electrical Engineering +14

Fault Models for Logic Circuits in the Multigate Era

Ajay N. Bhoj, Muzaffer O. Simsir, Niraj K. Jha · IEEE Transactions on Nanotechnology · 2011 · 36 citations

Engineering, Vlsi Design, Computer Architecture +17

Fault modeling for FinFET circuits

Muzaffer O. Simsir, Ajay N. Bhoj, Niraj K. Jha · 2010 · 33 citations

Device Modeling, Hardware Security, Electrical Engineering +13

Parasitics-Aware Design of Symmetric and Asymmetric Gate-Workfunction FinFET SRAMs

Ajay N. Bhoj, Niraj K. Jha · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2013 · 32 citations

Device Modeling, Electrical Engineering, Parasitics-aware Design +10