Steven Raasch - Concepedia

Author

Steven Raasch

University of Michigan ORCID

Also Known As

Raasch, Steven; Sadowski, Greg; Roberts, David A., S.E. Raasch, Steven E. Raasch, Steven Raasch

Publications

480

Citations

H-Index

Concepts

All Affiliations

University of Michigan Advanced Micro Devices (Canada)Los Alamos National Laboratory Sandia National Laboratories

About

Steven Raasch is an author at University of Michigan specializing in engineering, computer architecture, and computer engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	11	11	458
2	Computer Engineering	11	11	458
3	Computer Science	9	9	406
4	Electrical Engineering	2	2	52
5	Data Science	1	1	11

Steven Raasch

Publications

458

Citations

H-Index

Page 1

	Year	Citations
A scalable instruction queue design using dependence chains Steven Raasch, Nathan Binkert, Steven K. Reinhardt ACM SIGARCH Computer Architecture News Heterogeneous ComputingEngineeringDependence ChainsComputer ArchitectureNew Iq Design	2002	93
Design and Analysis of an APU for Exascale Computing Thiruvengadam Vijayaraghavan, Arun Karunanithi, Onur Kayıran, Cluster ComputingHeterogeneous ComputingEngineeringComputer ArchitectureSupercomputer Architecture	2017	72
The impact of resource partitioning on SMT processors Steven Raasch, S.K. Reinhardt Cluster ComputingHeterogeneous ComputingEngineeringComputer ArchitectureProcessor Throughput	2004	69
A scalable instruction queue design using dependence chains Steven Raasch, Nathan Binkert, S.K. Reinhardt EngineeringDependence ChainsComputer ArchitectureNew Iq DesignProcessor Architecture	2003	39
Applications of Thread Prioritization in SMT Processors Steven Raasch Heterogeneous ComputingEngineeringComputer ArchitectureMultithreading (Computer Architecture)Processor Architecture	1999	36
Integrating superscalar processor components to implement register caching Matthew A. Postiff, David Greene, Steven Raasch, Register CacheEngineeringCaching TechniqueComputer ArchitectureArchitectural Support	2001	36
On Characterizing Near-Threshold SRAM Failures in FinFET Technology Shrikanth Ganapathy, John Kalamatianos, Keith Kasprak, Hardware SecurityNon-volatile MemoryElectrical EngineeringEngineeringVlsi Design	2017	34
Compiler Techniques to Reduce the Synchronization Overhead of GPU Redundant Multithreading Manish Gupta, Daniel Lowell, John Kalamatianos, EngineeringGpu BenchmarkingComputer ArchitectureMultithreading (Computer Architecture)Gpu Redundant Multithreading	2017	29
A fast and accurate analytical technique to compute the AVF of sequential bits in a processor Steven Raasch, Arijit Biswas, Jon Stephan, Port AvfsAccurate Analytical TechniqueEngineeringHardware AlgorithmComputer Architecture	2015	21
Lifetime memory reliability data from the field Taniya Siddiqua, Vilas Sridharan, Steven Raasch, EngineeringMem TestingComputer ArchitectureSystem ReliabilityHardware Security	2017	18

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