PIM Lite: On the Road Towards Relentless Multi-threading in Massively Parallel Systems

Abstract

Processing In Memory (PIM) technology (mixing significant processing logic with dense memory on the same chip) has become a popular new emerging trend in recent years. In many cases, however, it has been used simply as a step towards a “system on a chip. ” This paper assumes that PIM systems will be inherently massively parallel, with many chips collaborating in a computation, perhaps in concert with more conventional microprocessors. While such systems could be designed to support “classical ” parallel models such as DSM or message passing, this paper discusses several different models born from the HTMT project. All of these models involved significant multi-threading, with large numbers of relatively light weight threads executing within the PIM nodes. To take advantage of these characteristics, we have designed a new ISA and matching microarchitecture that supports such multithreading in ways that leverage very efficiently the enhanced local bandwidth and access time capable from an on chip memory macro. A simplified version of this, termed PIM Lite, is about to go to fab as a memory part with multiple internal nodes, all of which support very light weight threads in a simple SMTmicroarchitecture. This paper will discuss PIM Lite, and then our outlook on what more advanced designs might look like. 1