PCIe 5.0 Connector Distributed Physical-Based Circuit Model With Loading Resonances for Fast SI Diagnosis and Pathfinding

Abstract

We report on the development of a fast signal integrity (SI) diagnosis and pathfinding tool for a Peripheral Component Interconnect Express (PCIe) 5.0 connector based on the distributed physical-based transmission line (dPBTL) circuit model. Frequency-dependent loading resonances due to add-in card (AIC) and baseboard (BB) are identified via HFSS field simulation and analysis. The subcircuit models for ground-cavity (GC) and stub-effect resonances are established and matched well with the field simulated. The integrated dPBTL accurately predicts differential-mode performances and resonant crosstalk up to 64 GHz, speeds up simulation by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5000\times $ </tex-math></inline-formula>, and reduces data storage by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.84\times 10^{6}$ </tex-math></inline-formula> compared with the traditional full-wave approach. Fast-guided and evaluated by 1-D dPBTL, design modifications reduce loading resonances and broadband dispersion, meeting PCIe 6.0 S-parameter requirements. Informed by dPBTL design, the 3-D pathfinding PCIe 6.0 connector demonstrates a 700% eye height (EH) enlargement and 150% eye width (EW) improvement at 64-GT/s non-return-to-zero (NRZ). Average 14% and 35% are improved in EH and EW for the three eyes at 64-GT/s (32-GBaud) PAM4. Furthermore, eye-openings at 128- and 144-GT/s PAM4 support further development toward PCIe 7.0 applications.