A 71.5-dB SNDR 475-MS/s Ringamp-Based Pipelined SAR ADC with On-Chip Bit-Weight Calibration

Abstract

This paper presents a 13-bit 475-MS/s single-channel pipelined SAR ADC, which utilizes a ring amplifier (ringamp) for residue amplification through an improved bias scheme and common-mode feedback (CMFB). Moreover, the ADC exploits an on-chip bit-weight calibration with signal-dependent pseudo-random noise (PN) injection and a window detector to correct the interstage gain error and DAC mismatch, requiring only 4096 PN-injected samples to calibrate the gain error in the background. As a result, this work achieves a peak SNDR of 71.5dB and consumes 9.93mW from a 1V supply. This corresponds to a state-of-the-art FoMs of 175.3dB and FoMw of 6.8fJ/conv-step.