2024 · 14 citations · 1 references
EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsLow-power DesignSystem-on-chip DesignAnalog Integrated CircuitsAnalog IntegrationLow-noise Circuit DesignMixed-signal Integrated Circuit DesignMixed-signal IntegrationNoise In Analog CircuitsAnalog Front-end CircuitsAnalog-to-digital ConversionAnalog-to-digital Converter DesignAnalog-to-digital Converter IntegrationAnalog-to-digital ConvertersComparator DesignDigital-to-analog Converter DesignLow-noise Analog Interfaces
We present a 60GS/s 7b 64-way Time Interleaved (TI) ADC with Analog Front End that features a non binary Partial Loop Unrolled (LU) SAR SubADC architecture which enables optimum comparator noise and power trade off. Comparator offsets among comparators of each SubADC are calibrated in background without analog hardware overhead by detecting patterns in the SAR output decisions. Fabricated in 5nm technology, the prototype AFE and ADC delivers 34.3dB SNDR till 32GHz and draws 109.3mW from 0.9V supply.
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VLSI'87: VLSI design of digital systems
Integration · 1989 · 134 citations
Engineering, Computer Engineering, Electrical Engineering +14