Interface States in Gate Stack of Carbon Nanotube Array Transistors

Abstract

A deep understanding of the interface states in metal-oxide-semiconductor (MOS) structures is the premise of improving the gate stack quality, which sets the foundation for building field-effect transistors (FETs) with high performance and high reliability. Although MOSFETs built on aligned semiconducting carbon nanotube (A-CNT) arrays have been considered ideal energy-efficient successors to commercial silicon (Si) transistors, research on the interface states of A-CNT MOS devices, let alone their optimization, is lacking. Here, we fabricate MOS capacitors based on an A-CNT array with a well-designed layout and accurately measure the capacitance-voltage and conductance-voltage (C-V and G-V) data. Then, the gate electrostatics and the physical origins of interface states are systematically analyzed and revealed. In particular, targeted improvement of gate dielectric growth in the A-CNT MOS device contributes to suppressing the interface state density (D_it) to 6.1 × 10¹¹ cm^-2 eV^-1, which is a record for CNT- or low-dimensional semiconductors-based MOSFETs, boosting a record transconductance (g_m) of 2.42 mS/μm and an on-off ratio of 10⁵. Further decreasing D_it below 1 × 10¹¹ cm^-2 eV^-1 is necessary for A-CNT MOSFETs to achieve the expected high energy efficiency.