Compact Dual-Core Drive Stage Using Three-Winding Transformer for CMOS Broadband Power Amplifier

Abstract

We present a novel broadband power amplifier (PA) architecture designed to achieve both high output power and a compact chip size in CMOS. This architecture features a dual-core drive stage and a compact vertical three-winding transformer (TF). Implemented using a 65-nm bulk CMOS process, precise measurements validate its feasibility. The measured 3-dB bandwidth (BW <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\text{3 dB}}$</tex-math> </inline-formula> ) of the proposed PA is 8 GHz (7–15 GHz), with a fractional BW (FBW) of 73%. In the 10–15-GHz range, it demonstrates 19–22-dB gain, 22–23.2-dBm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\mathrm{SAT}}$</tex-math> </inline-formula> , and 30 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\%$</tex-math> </inline-formula> –41.5% PAE (all under the same bias conditions). During testing at 10–15 GHz (FBW: 40%) with a 1-CC 64-QAM OFDM signal (all under the same bias conditions), the PA demonstrates an average output power of 15.6–17.1 dBm and an average efficiency of 11.8 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\%$</tex-math> </inline-formula> –18.4% at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 25-dB error vector magnitude (EVM) <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\mathrm{rms}}$</tex-math> </inline-formula> .