2024 · 17 citations · 25 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureFault-tolerant ComputingFault-tolerant SystemsAccelerator ArchitectureDeep LearningFault InjectionHardware AccelerationHardware Fault ToleranceReliable System DesignAcceleratorsDeep Learning AcceleratorsFault Injection MethodologyFault Tolerant ArchitecturesHardware Fault InjectionReliability AssessmentSafety-critical ArchitectureSystolic Arrays
Systolic array has emerged as a prominent archi-tecture for Deep Neural Network (DNN) hardware accelerators, providing high-throughput and low-latency performance essen-tial for deploying DNNs across diverse applications. However, when used in safety-critical applications, reliability assessment is mandatory to guarantee the correct behavior of DNN accelerators. While fault injection stands out as a well-established practical and robust method for reliability assessment, it is still a very time-consuming process. This paper addresses the time efficiency issue by introducing a novel hierarchical software-based hardware-aware fault injection strategy tailored for systolic array-based DNN accelerators. The uniform Recurrent Equations system is used for software modeling of the systolic-array core of the DNN accelerators. The approach demonstrates a reduction of the fault injection time up to 3 × compared to the state-of-the-art hybrid (software/hardware) hardware-aware fault injection frameworks and more than 2000 × compared to RT-level fault injection frameworks - without compromising accuracy. Additionally, we propose and evaluate a new reliability metric through experimental assessment. The performance of the framework is studied on state-of-the-art DNN benchmarks.
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SCALE-Sim: Systolic CNN Accelerator Simulator
Ananda Samajdar, Yuhao Zhu, Paul N. Whatmough et al. · arXiv (Cornell University) · 2018 · 194 citations · Full text
PyTorchFI: A Runtime Perturbation Tool for DNNs
Abdulrahman Mahmoud, Neeraj Aggarwal, Alex Nobbe et al. · 2020 · 121 citations