An Energy-Efficient Discrete-Time Delta–Sigma Modulator With Dynamic-Range Enhancement and Tri-Level CDAC

Abstract

This article presents a dynamic range (DR) enhanced discrete-time delta–sigma modulator (DTDSM) applied to the Internet of Things (IoT). It is based on an asynchronous 1.5-bit successive-approximation-resister (SAR) quantizer and a tri-level feedback capacitive digital-to-analog converter (CDAC), eliminating the dynamic element matching (DEM) overhead. The proposed DR enhancement (DRE) technique based on a variable threshold ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\text{TH}}$</tex-math> </inline-formula> ) allows the system to achieve maximum benefits at different input amplitudes. The system is configured in a high loop gain mode at small input amplitudes, providing the system with a stronger noise-shaping (NS) capability. The system is configured in the maximum stable amplitude (MSA) mode for large input amplitudes. In addition, we modified the working model of the cascoded floating inverter amplifier (FIA) in the weak inversion region. The prototype DTDSM is implemented in a 180-nm CMOS process, achieving a 94.7-dB DR and 92.4-dB signal-to-noise-and-distortion ratio (SNDR) at a 700-Hz bandwidth with only 2.3- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula> W power consumption. As a result, the Schreier figure-of-merit (FoM) for SNDR and DR is 177.2 and 179.5 dB, respectively.