Scaling-CIM: eDRAM In-Memory-Computing Accelerator With Dynamic-Scaling ADC and Adaptive Analog Operation

Abstract

This article presents Scaling-computing-in-memory (CIM), an energy-efficient embedded dynamic random access memory (eDRAM)-based in-memory-computing (IMC) accelerator with a dynamic-scaling readout for signal-to-quantization-noise ratio (SQNR) boosting and analog-to-digital converter (ADC) overhead reduction. It greatly saves the ADC cost by reducing the required number of ADC-bit and ADC operations by codesigning the algorithm and hardware. Scaling-CIM proposes three key features: 1) dynamic scaling ADC (DSA) boosts SQNR of multibit operation even with low-bit ADC; 2) adaptive analog bit-parallel (AABP) accumulation reduces the redundant ADC operation; and 3) layer-wise adaptive bit-truncation (LABT) search further enhances efficiency on benchmarks. The Scaling-CIM is fabricated in 28-nm CMOS technology and occupies a 2.03-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> die area with an 800-kb eDRAM cell. It achieves 39.7-TOPS/W (8–9 b) energy efficiency on the RestNet-18 benchmark and 1.96 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> higher efficiency figure of merit (FoM) than the previous IMC-based accelerator.