Negative-U Defect Passivation in Oxide-Semiconductor by Channel Defect Self-Compensation Effect to Achieve Low Bias Stress V_TH Instability of Low-Thermal Budget IGZO TFT and FeFETs

Abstract

In this work, we elucidate the fundamental bias stress reliability mechanism in oxide-semiconductor devices and provided guidelines to improve interface/bulk-induced V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</inf> degradation. We provide further insights into the defect-self compensation effect for the bilayer ITO-IGZO channel. Specifically, how our process approach led to effective passivation of channel defects such as negative-U defects, and ionized-oxygen-vacancy defects. With bilayer ITO-IGZO, we demonstrated 10x negative/positive bias stress (NBS/PBS), and 4x negative bias illumination stress (NBIS) improvement against the conventional mono-IGZO devices. Furthermore, under a low-thermal budget constraint, we implemented a sacrificial replacement gate stress memorization technique to enhance the ferroelectric phase to enable a double-gated (DG) IGZO FeFET. Our reliability-optimized DG ITO-IGZO FeFETs exhibit an enhanced memory window (MW) of 1.7V, excellent memory-write endurance of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> cycles, outstanding memory retention with high I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</inf> /I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</inf> of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> after 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> s, record-low NBS/PNS V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</inf> shift of 30mV, and NBIS V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</inf> shift of 110mV after stress time of 1000s. These devices set a new oxide thin-film transistor (TFT) reliability record making major strides toward highly reliable BEOL logic and memory switches.