A 0.5µm Pixel 3-layer Stacked CMOS Image Sensor with Deep Contact and In-pixel Cu-Cu Bonding Technology

Abstract

64Mp CIS with 0.5um pixels has been developed with three wafer layers (e.g. top-wafer for PDs and TG TRs, mid-wafer for pixel TRs, and bottom-wafer for the analog and logic circuits). The RTS noise was reduced by 85% compared to ones of the conventional structure with over 6,000e-FWC as similar to our previous research [1] - [3]. In addition, the FD conversion gain was improved by 67% with the Miller effect due to the reduction of the DCNT capacitance.