Real-Time FPGA-Based Implementation of Digital Predistorters for Fully Digital MIMO Transmitters

Abstract

This paper presents the hardware implementation of a real-time digital predistorter (DPD) for fully digital multiple-input multiple-output (MIMO) transmitters. The predistorter is comprised of a dual-input single-output (DISO) DPD module for each chain and a shared crosstalk and mismatch (CTMM) module that estimates the reflected wave back into each PA. The proposed real-time DPD is a DISO piece-wise linear (PWL) model implemented on a field-programmable gate array (FPGA) and achieves a linearization bandwidth up to 1.2 GHz at a clock rate of 300 MHz. The real-time DPD engine is demonstrated on a four-chain MIMO testbed and validated against a PC-based DPD engine. The FPGA-based DISO DPD performs within 1 dB ACPR of the PC-based implementation and achieves a similar root-normalized-mean-square error (RNMSE) of 1.59%.