A 3nm 256Mb SRAM in FinFET Technology with New Array Banking Architecture and Write-Assist Circuitry Scheme for High-Density and Low-V<sub>MIN</sub> Applications - Concepedia

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A 3nm 256Mb SRAM in FinFET Technology with New Array Banking Architecture and Write-Assist Circuitry Scheme for High-Density and Low-V<sub>MIN</sub> Applications

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2023

Year

Jonathan Chang, Yen-Huei Chen, Gary Chan, Kuo-Cheng Lin, Po‐Sheng Wang, Yangsyu Lin, Sevic Chen, Peijiun Lin, Ching-Wei Wu, Chih-Yu Lin,

Unknown Venue

Abstract

This paper presents a 3nm 256Mb SRAM in FinFET technology with interleaved triple WL scheme and new array banking architecture for low V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MIN</inf> applications.