How Fault-Tolerant Quantum Computing Benefits from Cryo-CMOS Technology

Abstract

Given the limited space and cooling capacity in dilution refrigerators, it is challenging to scale the number of qubits for a fault-tolerant quantum computer (QC). In this paper, we study a custom-scaled CMOS technology to overcome the constraints in the dilution refrigerators. With Cryo-Design/ Technology CoOptimization (Cryo-DTCO) in an advanced node, one can then reduce the control power from 26.8 mW/ qubit to 8.4 mW/ qubit $(\sim 0.31 \times)$. Projections suggest this may be sufficient to enable error corrections via surface codes for fault-tolerant computing.