A High-Speed Capacitor Less LDO with Multi-Loop Fast Feedback and Bandwidth Enhancement Control

Abstract

This paper presents a high-speed low dropout (LDO) regulator with wide dynamic range. The use of piecewise speed enhancement technique dividing the loop dynamic into three phases in which the current regulation circuits (CRC), large-signal derivative path control circuits addressing the design challenge of slew rate limitation, and the hybrid passive-active frequency compensation (PAFC) for small signal settling time improvements are introduced lends the proposed LDO to providing constant output voltage under the condition of large load variations. The LDO is designed in TSMC 180-nm 1.8 V standard CMOS technology with 0.17 mm2 active area. The quiescent current is 380 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mu \mathrm{A}$</tex> at no load. With regulated 1.2 V output, the input voltage ranges from 1.3 V to 1.8 V. The measured overshoot and undershoot with load steps of 0 to 100 mA at 50 ns edge time are 135 mV and 105 mV, respectively. The settling time at 25 mA, 50 mA and 100 mA are 2.6 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mu \mathrm{s}, 4.5\mu \mathrm{s}$</tex> , and 9.8 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mu \mathrm{s}$</tex> , respectively. The LDO is competent in handling a wide range of output capacitance from 0 to 5 nF while the overshoot and undershoot exhibits small variation in the load step response.