Development of 3-layer stacked global shutter CMOS image sensor with pixel pitch Cu-to-Cu interconnection and high-capacity capacitors

Abstract

We have successfully developed two kinds of novel 3-layer stacked backside-illuminated (BSI) voltage-domain global shutter (GS) CMOS image sensors (CIS) with consecutive void-free hybrid bonding processes. A new 3-layer stacked GS CIS contains the separate high-capacity capacitors on the middle wafer which are connected to pixel transistors via pixel-pitch Cu-to-Cu hybrid bonding, followed by another Cu-to-Cu hybrid bonding that connects middle capacitor wafer to bottom logic wafer. Another type of sensor architecture contains thinned Si layer in middle wafer that enables 3-dimensional (3D) integration of transistors for GS operation. Our proposed 3-layer stacking integrations provide a pathway to pixel-level integration of ultrahigh-capacity capacitors for further shrink of GS CIS.