A 0.45 mV/V Line Regulation, 0.6 V Output Voltage, Reference-Integrated, Error Amplifier-Less LDO With a 5-Transistor Regulation Core

Abstract

This article proposes a fully-integrated, error amplifier (EA)-less, reference-inbuilt, dual-loop low dropout regulator (LDO) working at a minimum input voltage of 0.7 V. The reference-integrated structure has a flipped-voltage-follower (FVF) as the output stage and provides an output voltage of 0.6 V. The dual-loop architecture provides high dc loop gain ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\geq $ </tex-math></inline-formula> 60 dB), a very small output impedance, along with the proposed load-adaptive-biasing (LAB), which results in excellent line and load regulation. The power supply rejection (PSR) of the proposed LDO is improved by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$&gt;$ </tex-math></inline-formula> 30 dB at frequencies around 100 kHz, using the proposed replica-based supply noise cancellation (RSNC). The design is fabricated in 0.18 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS technology and occupies an area of 0.074 mm2. The measured load and line regulation are 0.35 mV/mA and 0.45 mV/V, respectively, which are the best in the literature for sub-1 V LDOs. The minimum PSR till 1 MHz is −41.2 dB, and the design achieves a transient figure of merit (FoM) of 35.82 fs considering the limitation of having a low input voltage at a higher technology. This LDO achieves a 2.78 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> better line regulation and a 1.43 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> better load regulation compared to state-of-the-art sub-1 V LDOs while assuring a strong PSR performance till 1 MHz.