Control Development and Fault Current Commutation Test for the EDISON Hybrid Circuit Breaker

Abstract

The dc circuit breaker is an indispensable building block for dc network systems. Hybrid circuit breakers that combine mechanical and solid-state switches have more potential to be utilized in dc distribution networks because of their lower conduction losses and fast interrupt speed. The efficient energy dc interrupter with surge protection (EDISON) removes any solid-state circuit in the main current path, thereby substantially reducing the conduction losses during normal operations. However, it requires a dedicated control with fast dynamics because any false triggering of the mechanical switch or solid-state switches of the breaker would lead to a commutation failure and a potential unquenchable arc. This article proposes an FSM-based control scheme that guarantees the accurate and fast control response during a fault event. Due to this fast response requirement, a dual-core-CPU-based control architecture is applied featuring parallel taskings and negligible communication delays between the two cores. Furthermore, a control-law accelerator is employed to further reduce the latency of the program execution by 33%. The controller hardware-in-the-loop (CHIL) model of the EDISON breaker is implemented in OPAL-RT to verify the control scheme and derisk the prototype test. A fifth-order <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RLC</i> network is developed to characterize the mechanical switch behavior such that the hybrid circuit model can be simulated in the CHIL solely by circuit components. Finally, the proposed control scheme is implemented and validated in a prototype test with a 3 kA interrupting current and a 60 A/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">${\mu }$</tex-math></inline-formula> s current commutation rate.