A 1.8GHz 12b Pre-Sampling Pipelined ADC with Reference Buffer and OP Power Relaxations

Abstract

Direct RF sampling reduces complexity for receiver design. However, SNDR and speed specifications of its ADCs are stringent, which makes the time-interleaved (TI) ADC attractive for the required sampling rate. There is a tradeoff between single-channel performance and the complexity of TI calibration. The energy efficiency is also compromised by a high-speed single-channel ADC design. The TI SAR ADC [1] simplifies the single-channel architecture (SAR) with complex skew and inter-channel calibrations. Owing to the lack of a gain stage for noise relaxation, the comparator noise of a SAR ADC limits SNDR. With a gain stage implemented by the ring amplifier [2], the single-channel closed-loop pipelined ADC speed and SNDR are improved, relaxing the TI calibration. However, the high-power background calibration for the stringent OP finite gain error is inevitable. The pipelined SAR ADC with an open-loop amplifier [3] shows attractive specifications. However, the PVT variation degrades the system stability for the open-loop amplifier. This work proposes a 12b closed-loop pipelined ADC employing a pre-sampling (PS) technique, which achieves improved conversion efficiency by maximizing the closed-loop beta-factor, demonstrating a stable radix, and relaxing the reference drive requirements. The resultant <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{FoM}_{\mathrm{W}}$</tex> is 5.06-fJ/c.-s. at the 1.8GHz sampling rate and SNDR of 60.16dB.