Capacitor Mismatch Calibration of a 16-Bit SAR ADC Using Optimized Segmentation and Shuffling Scheme

Abstract

This brief presents a 16-bit successive approximation register (SAR) analog-to-digital converter (ADC) with input- signal-independent background calibration. A serial double conversion (SDC) method with second MSB decisions skipped is proposed to perform A/D conversion and background calibration simultaneously, with only one ADC and little extra time. Deep and input-signal-independent calibration is achieved with the proposed optimized segmentation and shuffling (OSAS) scheme, which uses customized shuffling and paired-swapping to inject only the weight error of DAC capacitors into the residue, including the bridge capacitor. In addition, by making the shuffling process more flexible, the OSAS scheme speeds up the convergence of calibration. The proposed calibration is experimentally validated on a prototype 16-bit SAR ADC fabricated in 180-nm CMOS technology, demonstrating an SFDR and SNDR improvement of 30.2 dB and 25.3 dB at 1-MS/s, respectively, and the calibration converged after only 3,000 samples.