A High-Speed Low-Noise Comparator With Auxiliary-Inverter-Based Common Mode-Self-Regulation for Low-Supply-Voltage SAR ADCs

Abstract

A high-speed low-noise comparator with an auxiliary inverter-based (AIB) preamplifier is proposed in this brief. The preamplifier adopts an inverter-based input pair without tail transistors, which is well-suitable for low-supply-voltage applications, especially in deep submicrometer technologies. Moreover, it achieves high bandwidth and low noise with high current efficiency. Dynamic common-mode feedback combined with a secondary inverter-based input pair regulates the output common-mode (CM) voltage of the preamplifier by itself against PVT and input CM voltage sensitivity without complex control logic and quiescent current. Embedded in a 200 MS/s 16-bit successive-approximation-register (SAR) analog-to-digital converter (ADC) in standard 28-nm CMOS technology, the proposed comparator achieves a 68.1-ps delay at a 50- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{V}$ </tex-math></inline-formula> differential input voltage and a root-mean-square input-referred noise of 45.6 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{V}_{\mathrm {rms}}$ </tex-math></inline-formula> under the 1-V power supply.