Energy-Efficient High Bandwidth 6T SRAM Design on Intel 4 CMOS Technology

Abstract

In this article, we present an energy-efficient high bandwidth array design using 0.0300- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}^{2}$ </tex-math></inline-formula> high-performance SRAM bitcell on Intel 4 CMOS technology. By employing a unique combination of design techniques–column mux (CM) of 1, flying BL (FBL), passive write assist scheme, and energy-efficient column design–the proposed 6T SRAM array design demonstrates >80% access energy improvement over a conventional four-way interleaved 6T SRAM array design and 30% macro density improvement compared to a hierarchical bitline (BL) 8T SRAM design for high bandwidth memory applications.